Docs / Overview
Documentationv0.5.0
Everything you need to build, run, and understand SynapticOS — from a first QEMU boot to the flash partition map of the OTA design. The documentation tracks the code: pages marked v0.5.0 describe what shipped in Phase 5, pages marked v0.4.0 and earlier are unchanged since those phases, and what arrives in later phases is labeled with its target version.
Start here
- Installation & workspace — one west workspace, two targets (QEMU and FRDM-MCXN947).
- Flash the FRDM-MCXN947 — the blhost ISP flow, step by step.
- Hello Inference in 20 lines — the full pipeline in one small program.
- The syn shell — inspect the runtime over serial, no JTAG required.
How the docs are organized
Concepts explains the architecture — why the runtime is organized around the inference pipeline, how the tensor arena eliminates fragmentation, what the HAL state machines guarantee, and how the two Cortex-M33 cores divide the work.
API reference covers all eleven public headers under include/synaptic/ — the ten frozen Phase 1 headers plus syn_process.h, added in Phase 2 for the built-in processor configs. The reference documents exactly what ships.
Configuration lists every CONFIG_SYNAPTIC_* Kconfig symbol with defaults and valid ranges.
Guides are task-oriented: running the 158-test suite, profiling an inference end to end, the five samples, and porting to a new board.
The latest release is v0.5.0 (Phase 5, Production Hardening) of a six-phase roadmap: the runtime now dispatches by priority and deadline, preempts layered jobs at layer boundaries with bit-exact resume (10 µs context save), places DAG activations memory-optimally (−43% peak on the demo DAG), supervises itself with a hardware watchdog and a CPU1 heartbeat (hang recovery demonstrated live), ingests frames zero-copy over the eDMA (+251% vs CPU copy), and moves OTA images over a raw binary transport at 11.1 KB/s — 98.7% of the 115200 line rate — all verified on the FRDM-MCXN947 on 2026-08-09/10, passing the 158-test QEMU suite with 83.7% line coverage of the QEMU-buildable core, then soaked for 11,106 jobs with zero errors. Phase 6 (Ecosystem & Tooling) is next. The NPU backend remains a deterministic stub until the Neutron SDK integration — every inference figure is labeled accordingly — and the original 10 s/500 KB OTA target stays out of reach at 115200 baud by construction (reported as measured).