Research — SynapticOS

// Research

Publications.

Every result ships twice: the full preprint on arXiv, and an executive summary here — the argument in five minutes, the evidence in the paper.

P·01 · Foundation · Phase 1

SynapticOS: An Inference-First Runtime Architecture for Neural Processing Units on Resource-Constrained Microcontrollers

D. KAFETZIS · 2026 · ARXIV cs.AR / cs.SE · 10 PAGES · 5 FIGURES

Why the RTOS abstractions inherited from control systems fail inference workloads — and the measured case for a runtime where the tensor pipeline comes first.

Executive summary arXiv — on publication

P·02 · In preparation

Zero-Copy Tensor Pipelines and Layer-Boundary Preemption on MCU-Class NPUs

BUILDS ON THE v0.2.0 PIPELINE ENGINE · NEUTRON SILICON MEASUREMENTS PENDING SDK INTEGRATION

P·03 · In preparation · Phase 3 shipped

Asymmetric Dual-Core Inference Serving over Shared-Memory IPC

v0.3.0 BOARD-VERIFIED · CPU1→CPU0 ROUND-TRIP 15 µs TYPICAL / 81 µs WORST-CASE

P·04 · In preparation · Phase 4 shipped

Power-Loss-Safe Over-the-Air Model Updates as an Operating-System Service on Dual-Core Microcontrollers

v0.4.0 BOARD-VERIFIED · REGISTRY COMMIT 1.9–2.6 ms · 432 KB OTA STAGED, VERIFIED & ACTIVATED · POWER-LOSS INJECTED ON HARDWARE

P·05 · In preparation · Phase 5 shipped

Layer-Granularity Inference Preemption, Memory-Optimal Activation Planning, and Fault Recovery as Operating-System Services on Dual-Core Microcontrollers

v0.5.0 BOARD-VERIFIED · 10 µs CONTEXT SAVE, BIT-EXACT RESUME · −43% ACTIVATION PEAK · WATCHDOG RESET + CPU1 HANG RECOVERY DEMONSTRATED · 11,106-JOB SOAK, 0 ERRORS · STUB-NPU LABELED