Inference is the primary workload.
Not an add-on.
SynapticOS is an inference-first runtime for microcontrollers with neural accelerators — built on Zephyr RTOS. Memory, scheduling, and hardware abstraction are all designed around one thing: the data flow of a neural network.
Most RTOS platforms treat AI inference as an afterthought.
The status quo
A neural inference library bolted onto a scheduler that was designed for control loops and sensor polling. On microcontrollers with dedicated NPUs, that mismatch wastes silicon.
The NPU sits idle while the CPU copies buffers. The memory allocator fragments the heap under tensor churn. And there is no clean way to manage model lifecycles or pipeline data from sensor to prediction.
The SynapticOS answer
- >_The scheduling unit is the inference jobPriority- and deadline-aware, preemptable at NPU layer boundaries — not a generic thread.
- >_Tensor-aware memory, zero fragmentationA bump allocator with persistent, ephemeral, and scratch regions — DMA-aligned by construction.
- >_Hardware-agnostic accelerationOne HAL for NPU, DSP, and DMA. The same application runs on Neutron silicon or a deterministic QEMU stub.
- >_Models are a managed lifecycleVersioned, registered, hot-swappable — persisted in flash with power-loss-safe A/B OTA updates and rollback, verified on the board.
Every subsystem serves the pipeline.
Eleven public headers (ten frozen since v0.1.0), one syn_ API, roughly 6,000 lines of C on top of Zephyr v3.7.0.
syn_mem.hTensor memory arena
O(1) bump allocation over fixed SRAM: persistent weights, ephemeral activations, isolated scratch.
syn_hal_npu.hNPU HAL
Explicit IDLE / BUSY / ERROR / SUSPENDED state machine wrapping eIQ Neutron — or a deterministic stub in CI.
syn_hal_dsp.hDSP HAL
Normalize, softmax, argmax, FFT on the PowerQuad coprocessor, with software fallbacks.
syn_infer.hInference scheduler
Pipelines as first-class jobs: priority + earliest-deadline dispatch with preemption at layer boundaries and bit-exact resume (10 µs context save on the board).
syn_model.hModel registry
Register, load, invoke, hot-swap. Metadata with versions, tensor shapes, CRC32, memory budgets.
syn_prof.hProfiler
Cycle-accurate per-stage timing, peak memory, NPU utilization. Zero overhead when disabled.
syn_ipc.hInter-core IPC
Lock-free shared-memory rings between the app core and the AI core — 15 µs typical round-trip, measured on the board.
syn_shellDeveloper shell
Runtime introspection over serial — no JTAG required. syn mem, syn model, syn npu, syn prof.
Each pipeline stage maps to dedicated silicon — the CPU orchestrates, it doesn't copy.
The OS talks back.
Verbatim serial capture from a FRDM-MCXN947 over MCU-LINK — boot to interactive shell in about a millisecond.
This terminal is live — click it and type help; responses mirror the v0.5.0 release (2026-08-10 board verification, dual_model sample — try syn health or syn infer stats). · Transcript above: 2026-07-14 v0.3.0 board verification · stub NPU backend (Neutron SDK integration lands in a later phase)
Runs on a $15 board.
The NXP FRDM-MCXN947 — two Cortex-M33 cores, a neural accelerator, a DSP coprocessor, and smart DMA. SynapticOS assigns each one a job.
| Board | NXP FRDM-MCXN947 |
| CPU | 2× Arm Cortex-M33 @ 150 MHz |
| NPU | eIQ Neutron · 4.8 GOPS INT8 |
| DSP | PowerQuad coprocessor |
| Memory | 512 KB SRAM · 2 MB dual-bank flash |
| Price | ~$15 USD |
15 µs measured
Six phases to v1.0.
Open source now, engineered like a product. Phases 1 through 5 have shipped — all verified live on the FRDM-MCXN947 and tagged as releases. Next up: Phase 6, ecosystem and tooling toward v1.0.
Built in the open — argued on paper.
SynapticOS: An Inference-First Runtime Architecture for Neural Processing Units on Resource-Constrained Microcontrollers
D. KAFETZIS · ARXIV PREPRINT · cs.AR / cs.SE — publishing with Phase 1
The foundation paper makes the architectural case: why the RTOS abstractions we inherited from control systems fail inference workloads, and what a runtime looks like when the tensor pipeline comes first. Every number is measured, and stub-baseline results are labeled as exactly that.
C·1Tensor-aware memory architecture — lifetimes as regions, not a heapC·2State-machine HAL for NPU + DSP with deterministic fallbacksC·3Model lifecycle registry with versioning and integrity checksC·4Integrated profiling at inference-pipeline granularityC·5Open implementation — ~4,100 lines of C, Apache-2.0
Open source now.
Built to grow.
Clone it, build it for QEMU in one command, flash it to a $15 board. Contributions open in an upcoming phase — until then, stars, issues, and hard questions are very welcome.