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An inference-first runtime for NPUs on resource-constrained microcontrollers

DIMITRIOS KAFETZIS · 2026 · ARXIV PREPRINT (cs.AR / cs.SE) · SUMMARY ≈ 6 MIN · PAPER 10 PP

If a microcontroller ships with a neural accelerator, why is its operating system still organized around threads and a heap? The foundation paper makes the architectural case for reorganizing the runtime around the inference pipeline — and measures what that buys on a $15 board.

Why it matters

MCU-class NPUs like NXP's eIQ Neutron deliver 4.8 GOPS of INT8 compute, but the software stack around them was designed for control loops: general-purpose schedulers, fragmenting heap allocators, and no notion of a model as a managed resource. The result is idle silicon — the accelerator waits while the CPU copies buffers. SynapticOS restructures the runtime so that memory regions match tensor lifetimes, accelerator state is explicit, and the scheduling unit is the inference job itself.

1,038 µsEnd-to-end · FRDM hardware
65 KBFlash · full runtime + shell
~154 cycPer allocation · size-invariant

The five contributions

Key figure — the tensor arena

SCRATCH
16 KB

FIG. 2 — Two bump pointers advance toward each other inside the 112 KB tensor region; the scratch pool is physically isolated so a preprocessing overrun can never corrupt weights. Allocation is O(1) — no free list, no fragmentation, ever.

Honest limits

All Phase 1 latency figures are measured against the deterministic stub backend — they characterize runtime overhead, not Neutron silicon throughput. That is stated plainly in the paper, and the follow-up work measures the real accelerator once the eIQ Neutron SDK integration lands.

Cite this work

bibtex
@misc{kafetzis2026synapticos,
  title  = {SynapticOS: An Inference-First Runtime Architecture for Neural
            Processing Units on Resource-Constrained Microcontrollers},
  author = {Kafetzis, Dimitrios},
  year   = {2026},
  note   = {arXiv preprint}
}